Thunderbolt I/O technology was developed by Intel. Each interface is equipped with two 10Gbps full-duplex data path links, which is up to 12 times faster than the Firewire800 interface. Thunderbolt uses 64b/66b data encoding format, and the interface controller developed by Intel can multiplex PCI–Express and DisplayPort into a single data stream. The controller developed by Intel is code-named Light Ridge, the subsequent second- and third-generation controllers are code-named Cactus Ridge and Redwood Ridge respectively, and the new generation (fourth-generation) controller is code-named Falcon Ridge.
In the host device, the controller obtains PCI–Express data from the I/O controller hub and DisplayPort data from the negative signal in the I/O controller or from an external graphics controller as shown in Figure 1. Next, this combined signal is sent out via full-duplex differential signaling. Typically, each controller is equipped with two ports that can be connected in a daisy chain.
A brief explanation of Thunderbolt interface definition
The first two generations of Thunderbolt used the mini DP interface, while Thunderbolt 3 started using the Type-C physical interface, which has 20 pins.
As shown in the picture. Among them, Ground is all grounded, with a total of 8 wires, 2 of which are reserved unused. Pin 2 is used for hot plug testing, pins 3 to 6 are a pair of bidirectional serial differential signals, and pins 15 to 18 are another pair of bidirectional serial differential signals. Therefore, Thunderbolt 1 is based on PCI-E 2.0 Pins 9 and 11 are probably USB 2.0 differential signals (aka "backwards compatible with USB"). Pin 20 is the positive power supply. Regarding Thunderbolt 2, the official speed is 20Gbps, based on PCI-E 2.0 X4, and still uses the miniDP interface (the interface definition remains unchanged, so it is fully compatible). However, according to the interface definition, miniDP can only carry 4 differential signals, that is, two pairs (X2 channel) under full duplex
Because 4 channels can work in one direction at the same time, the speed can reach the one-way speed of PCI-E X4, which is 20GT/s, but it is half-duplex at this time. In full duplex, the one-way speed is still 10GT/s. Next up is Thunderbolt 3. Thunderbolt 3 uses the Type-C interface that we are all very familiar with. The definition of the Type-C interface in USB is as follows
However, Thunderbolt 3 has 4 differential signals, so the pin definition is completely different from USB3.1 (2 differential signals). Unfortunately, I didn't find the information on how to define it specifically. But we can make a general analysis. Type-C has 24 pins, but because it is reversible, only half of the pins are active, which is the part circled in the picture.
So, there are 12 pins available. These 12 pins are allocated to 4 differential signals, requiring 8 pins. In addition to 1 shielding ground, 1 ground wire, 1 power supply (positive pole), and one remaining wire (may be used for hot plug detection), it is completely sufficient. In terms of protocol, full-speed Thunderbolt 3 uses PCI-E3.0 X4, which is divided into two modes like Thunderbolt 2 - full-duplex and half-duplex. Under half-duplex, the speed is 32GT/s. Because 128b/130b encoding is used, the actual speed is 3.938GB/s (you can know it by looking up the table). Of course, the speed is halved in full-duplex mode. Then I am very curious - where does the official promotional speed of "40Gbps" come from? My personal guess is that Intel, which has lost its moral integrity, is deceiving people again. 3.938, rounded up, it’s 4! Then according to the old 8b/10b encoding method (actually the encoding method has been changed), 4*8* (10/8) = 40G/s, well, there is nothing wrong with it. In addition, there is a half-speed version of Thunderbolt 3, which uses PCI-E 3.0 At half speed, there is actually no difference between the speed and full speed in full duplex. Note: The reason why the Thunderbolt 3 interface speed cannot reach the full speed of PCI-E 3.0 , can only accommodate 4 differential signals (while PCI-E 3.0 X4 has 8 differential signals). in conclusion. Thunderbolt is relatively advanced in principle. It uses four differential channels to achieve the unidirectional speed of PCI-E X4. Anyway, consumers don't care whether it is full-duplex or half-duplex. Personally, I think this design is a complete waste for PCI-E. In the Thunderbolt 3 era, where the speed has reached "20G/s in both directions", just to compete with USB3.1, the originally full-duplex PCI-E X4 was turned into half-duplex to solve the problem of insufficient line count. Problem, this is a serious waste (indeed, in order to find the 20 PCI-E 3.0 required for 4 full-speed Thunderbolt 3, the 2017 version of the high-end MBP uses 16 for independent graphics and 16 for PCH (which can be understood as South Bridge ) are all Thunderbolt, so it doesn’t even have a discrete graphics card! This is really a “Macbook Pro”! It doesn’t even have a discrete graphics card. Apart from the price, I really don’t see how it deserves the word Pro.
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